The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
An all-digital phase locked loop (ADPLL) is a PLL having a digital phase detector, a digital loop filter, and a digitally-controlled oscillator. An ADPLL has beneficial aspects over analog PLLs in view of small circuit area, testability, and programmability. A conventional ADPLL includes a time-to-digital converter (TDC), a frequency divider, and a digitally-controlled oscillator (DCO). When the DCO generates an output clock signal, the frequency divider divides the output clock signal by a predetermined dividing factor, and the TDC measures a phase difference between the divided clock signal and a reference clock signal. A finite resolution of the TDC leads to a quantization error, and thus increases an overall phase noise of the ADPLL.